PB6800, KGD测试分选系统, SiC, GaN, KGDHandler

Industry Context & Throughput Bottlenecks
As the electric vehicle (EV) industry rapidly evolves, Silicon Carbide (SiC) has firmly established itself as the core component for EV traction inverters. However, scaling up to High-Volume Manufacturing (HVM) presents several critical challenges for the industry:
Blind Spots in Static Testing: Traditional DC testing struggles to screen for sub-micron defects. A mere 10% alignment deviation can reduce the Short-Circuit Withstand Time (SCWT) by 0.5 µs.

The Microsecond Margin of Error: The SCWT of SiC devices is astonishingly short—typically just 2 to 7 µs. Exceeding this critical window easily triggers thermal runaway or instantaneous device destruction.

Dual Pressure from Costs and Standards: To eliminate a 2% to 3% field failure rate, the automotive industry now heavily mandates dynamic testing. Performing early screening at the Known Good Die (KGD) stage is crucial, as it avoids up to 3x the sunk costs associated with post-packaging failures.
The 1,500 UPH Throughput Ceiling: Driven by HVM demands, legacy single-die handlers—constrained by their mechanical limitations—max out at approximately 1,500 units per hour (UPH). A revolutionary architectural breakthrough is urgently needed.

Core Technologies & Breakthrough Solutions

To shatter this throughput barrier, the NexusTest PB6800 introduces a next-generation, high-parallelism dual-die architecture combined with a hybrid turret-track design:

High-Parallelism Dual-Die Architecture: Featuring a 6-site parallel configuration, the dual-die sockets allow two chips to be tested simultaneously per touchdown. This exponentially multiplies test throughput, fully satisfying HVM requirements.

Hybrid Turret-Track Design: This design successfully achieves "station decoupling." The rotary turret is dedicated exclusively to rapid loading, unloading, and sorting, while the linear track drives high-speed electrical testing, ensuring the die reaches complete thermal equilibrium prior to the actual test.
Ultimate Hard-Docking Integration: The rigid docking between the tester and the handler eliminates traditional cable loops. This strictly controls AC stray inductance to under 40 nH, effectively preventing destructive voltage overshoots during fast switching.
N₂-Purged Anti-Arcing Sockets: Utilizing a sealed Nitrogen (N₂) micro-environment elevates the breakdown voltage threshold. This completely eradicates arcing during 3,000V high-voltage stress testing, while keeping the environment dry and preventing probe contamination.

Performance Results & Throughput Leap
Through comprehensive system optimization and cycle-time decoupling, this novel test architecture achieves a quantum leap in performance:

Consistently delivers an ultra-high throughput of 4,000 UPH(based on a 0.7-second test time).

Seamlessly integrates with multiple carrier formats (Wafer, Tape & Reel, Tray) and supports up to 6 independent Tape & Reel output stations.
Highly integrated with 6-sided Automated Optical Inspection (AOI), alongside auto-socket cleaning and replacement functionalities, enabling fully automated, highly efficient continuous operation.

Conclusion
By implementing dual-die sockets to double testing density, utilizing hard-docking to keep loop inductance below 40 nH, leveraging an N₂ micro-environment to eliminate high-voltage arcing, and deploying a hybrid design to isolate mechanical bottlenecks, NexusTest has redefined the limits of SiC testing.
This suite of innovations not only shatters the legacy 3,000 UPH ceiling but establishes a new industry benchmark of 4,000 UPH. Ultimately, it provides the EV traction inverter market with a robust, zero-defect standard for the mass-production screening of SiC Known Good Die.